In the past, in a multi-processor system including a plurality of processor elements and a shared cache memory, processors and the shared cache memory are connected by a network including a plurality of routers (see Japanese Patent Application Laid-Open No. 2009-54083). The shared cache memory is connected to an external memory via a bridge.
In such a multi-processor system, accesses by the processor elements reach the shared cache memory respectively through the several routers. In this case, because all the memory accesses are concentrated on the shared cache memory, usually, loads on the routers to which the shared cache memory is connected increases, which is a bottleneck for an entire network.
Japanese Patent Application Laid-Open No. 2000-20489 discloses that a cache memory is provided in a communication control device, which relays data transfer between a CPU and an external apparatus, and transfer control information written by the CPU in a descriptor of a main storage unit is read out and written in the cache memory, whereby efficiency of data transfer between the CPU and the communication control device is realized. However, even if the invention disclosed in Japanese Patent Application Laid-Open No. 2000-20489 is applied to the routers of the multi-processor system, the routers access the shared cache memory and the external memory to write data in the cache memory. Therefore, the problem of the increase in the loads on the routers connected to the shared cache memory is not solved.